1. Field of the Invention
This invention relates to a semiconductor memory device such as a dynamic random access memory device (DRAM) and static random access memory device (SRAM) which has an internal address generator incorporated therein.
2. Description of the Prior Art
Generally, a semiconductor memory device is provided with an internal address generator incorporated therein. In a final manufacturing stage of a semiconductor memory device or in a suitable occasion after a memory device has been installed in an electronic apparatus, it is usual to conduct a test to check whether or not such an internal address generator operates normally. Conventionally, such a test is performed as follows: First, certain data is written in every bit of a memory device using addresses generated by the internal address generator. Then the written in data is sequentially read out using external addresses. The read out data is compared with the data that is expected from the corresponding address (i.e., that certain data). If all the read out data agrees with the expected data, it is judged that the internal address generator operates normally.
The prior art involves a problem in that it requires a prolonged period of time to conduct the test. In the prior art, furthermore, even when disagreement between the read out data and the expected value is detected, it is incapable of determining whether the cause of this failure lies in the internal address generator or in other circuitry of the memory device.